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1. Motivations & Learning Outcomes
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2. How to Take this Course
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3. Electrical Fluid
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4. Transmitting Electrical Fluid
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5. Reviewing the Atomic Model
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6. Conductors & Insulators
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7. Electron Spin
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8. Electron Flow & Hole Flow
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9. Conventional Current & Resistance
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10. Measuring Voltage with a Multimeter
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11. Limiting Current using Resistors
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12. Breadboard Internal Connections
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13. LED & Resistor on a Breadboard
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14. Autodesk TinkerCad
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15. Simulating Simple Circuits
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16. Path Lower Resistance
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17. Some Notes on Circuit Analysis
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18. Units of Measurement
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19. The Speed of Electricity
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20. Prefixes & Conversions
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21. Electric Field
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22. Telephone Networks & Switchboards
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23. Electricity & Magnetism
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24. Interactive Visualizations on Magnetism
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25. Relays
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26. AC vs DC
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27. Inductors & Transformers
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28. Capacitors
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29. Capacitors & Supply Interruptions
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30. LED & Capacitor on a Breadboard
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31. Diodes & Polarity Protection
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32. Rectifiers & Smoothing Capacitor
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33. Relays & Boolean Logic
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34. Analog vs Digital Electronics
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35. Logic Gates (AND, OR, & NOT)
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36. Relay Gates (AND, OR, & NOT)
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37. Thermionic Emission
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38. Vacuum Tube Diode
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39. Vacuum Tube Triode
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40. Analog Signal Amplification
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41. Semiconductors & Doping
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42. N-Type & P-Type Semiconductors
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43. PN Junction
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44. Transistors
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45. NPN Transistor
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46. Transistors & Amplification
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47. BJT 2N2222 on a Breadboard
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48. Logic Gates & BJT Transistors
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49. AND Gate using Transistors
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50. OR Gate using Transistors
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51. NOT Gate using Transistors
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52. NAND Gate using Transistors
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53. Are NAND Gates Easier to Build
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54. XOR Gate using Transistors
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55. SR Latch
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56. SR Latch using NOR Gates
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57. Active High & Active Low
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58. SR Latch using NAND Gates
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59. Gated SR Latch
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60. Gated D Latch
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61. Clocked D Latch
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62. Preset & Clear Inputs
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63. Crystal Clock
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64. Master-Slave D Flip-Flop
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65. JK Flip-Flop
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66. T Flip-Flop
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67. Binary Counter (Exercise)
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68. Implementing a Binary Counter
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69. Registers
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70. CD4014 IC Chip
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71. Hierarchies & Subcircuits
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72. Write Enable
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73. Half Adder
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74. Sum of Products
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75. SoP Simplifications
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76. Full Adder
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77. 8-Bit Adder (Exercise)
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78. Adding Two Bytes
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79. 7-Segment Display Driver
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80. Double Dabble Algorithm
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81. Why Doubling & Why Dabbling
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82. Designing a Dabble Chip
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83. Designing a Double Dabble Circuit
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84. Implementing NOT using NANDs
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85. Implementing AND using NANDs
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86. Implementing OR using NANDs
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87. Implementing XOR using NANDs
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88. Completing our 8-Bit Adder
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89. Two's Complement
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90. Converting Positive to Negative
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91. Subtracting Two 8-Bit Numbers
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92. The Bus
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93. Tri-State Logic
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94. Controlled Buffer in Logisim
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95. Connecting ALU to Bus
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96. Diode Matrix ROM
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97. Binary-to-Decimal Decoder
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98. Fixing a Small Decoder Mistake
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99. Memory Cells using Latches
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100. Reading a Word from Memory
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101. Read Enable Input
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102. Types of ROM
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103. Combinational Circuits vs ROM
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104. Writing to Memory Addresses
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105. Implementing 16 Bytes of RAM
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106. Addressing Rows & Columns
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107. 74LS219 & 74F189 RAM ICs
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108. SRAM vs DRAM
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109. Custom RAM Circuit Appearance
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110. Connecting MAR & RAM to Bus
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111. Connecting Registers & ALU to Bus
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112. Exercise Manually Storing RAM Values
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113. Manually Storing RAM Values
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114. Von Neumann Architecture
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115. Program Instructions
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116. Output Register
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117. Instruction Register & Program Counter
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118. Fetch-Execute LDA Instruction
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119. Fetch-Execute ADD Instruction
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120. Fetch-Execute OUT Instruction
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121. Programming Instructions in RAM
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122. Manually Executing Micro-Instructions
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123. Malvino's SAP-1 Computer
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124. Control Unit Sequencer
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125. Ring Counter
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126. Instruction Decoder
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127. Control Unit Inputs & Outputs
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128. Changing PC Appearance
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129. CU Logic for the Fetch Cycle
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130. CU Logic for the LDA Instruction
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131. CU Logic for ADD & OUT Instructions
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132. Halting the Control Unit
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133. Resetting the CPU
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134. Adding More CPU Instructions
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135. Microinstructions for SUB, STA, & JMP
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136. Programming the Loop Program
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137. Running our First Loop Program
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138. Computers & Computability
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139. Turing Completeness
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140. 16-Bit Long Instructions
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141. Instruction Register Hi & Lo Bytes
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142. Implementing 256 Bytes of RAM
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143. Changing our RAM Circuit Design
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144. Increasing Ring Counter Steps
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145. Storing CU Logic in ROM
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146. Encoding TSteps in Binary
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147. Testing our ROM Addresses
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148. Logisim's ROM Text File Format
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149. A Spreadsheet of CU ROM Values
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150. A Python Script to Export ROM
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151. Connecting All CU Signals
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152. Visualizing TSteps using LEDs
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153. Hardwiring CU Signals for T0 & T1
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154. Loading Instructions using Hex
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155. Running our Code with the CU ROM
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156. Removing T0 and T1 from ROM
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157. Exercise Adding Steps T8 and T9
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158. Adding Steps T8 and T9
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159. ALU Operation Selection
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160. New ALU & Branch Instructions
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161. Our New ALU Logisim Component
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162. Exercise Bitwise AND
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163. Bitwise AND & ALU Op Decoder
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164. Bitwise OR, XOR, & NOT
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165. Shifting Bits Right & Left
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166. Zero, Negative, & Carry Flags
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167. ALU Ops Microinstructions
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168. Including ALU Ops in our CU ROM
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169. Processor Status Flags Register
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170. Using Flags in our CU Logic
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171. Jump Condition Ops
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172. Decoding Condition Ops
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173. Matching Condition Ops & Flags
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174. Adding BRK to ALU Ops
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175. Exercise Even & Odd Numbers
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176. Code to Test Even & Odd Numbers
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177. Step by Step Even & Odd Code
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178. Exercise Countdown Loop
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179. Countdown Loop Assembly Code
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180. Exercise Fibonacci Sequence
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181. Fibonacci Sequence in Python
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182. Fibonacci Sequence Assembly Code
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183. Writing a Simple Assembler
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184. Reading Command Line Args
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185. Collecting All Labels
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186. Generating Machine Code
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187. Assembling our Fibonacci Code
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188. ADD & SUB Immediate
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189. Countdown Loop using SUB Immediate
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190. Absolute vs Relative Jumps
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191. Working with Multiple Registers
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192. Benefits of Multiple Registers
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193. Register File
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194. RISC vs CISC
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195. Instruction Pipeline
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196. Digital Logic Circuit Technologies
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197. MOSFETs
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198. N-Channel MOSFET
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199. P-Channel MOSFET
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200. Enhancement vs Depletion Mode
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201. CMOS
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202. Conclusion & Next Steps
